The invention relates to low drop out (LDO) voltage regulators, and more particularly to improvements therein which make voltage regulator respond better than prior LDO voltage regulators to output overvoltages caused by rapid load current transients.
FIG. 1 illustrates a low drop out voltage regulator which is believed to be representative of the closest prior art, described in detail in U.S. Pat. No. 5,864,227, by Borden et al. The voltage regulator shown in prior art FIG. 1 includes a P-channel output transistor MPX having its source connected to an unregulated voltage input Vcc and its drain connected to a regulated output voltage V.sub.OUT. (The "output" transistors referred to herein also are commonly referred to as "pass" transistors.) Its gate is connected to an error amplifier A1 having its (-) input connected to V.sub.REF and its (+) input connected to a feedback voltage V.sub.FB produced by a voltage divider R1,R2. A discharge circuit PD1 includes a P-channel discharge transistor MPD having its source connected to V.sub.OUT and its drain connected to ground. The discharge circuit PD1 includes a comparator C1 having an output connected to the gate of discharge transistor MPD. The (-) input of comparator C1 is connected to the output of error amplifier A1, and the (+) input of comparator C1 is connected to a reference voltage V.sub.TRIP, which is offset from ground by a suitable amount.
Comparator C1 compares the voltage applied by error amplifier A1 to the gate of output transistor MPX to V.sub.TRIP to determine whether or not error amplifier A1 is "in control" of its output, or whether error amplifier A1 has "saturated" in attempting to turn output transistor MPX off. If the output of error amplifier A1 exceeds V.sub.TRIP, the LDO voltage regulator "assumes" that a V.sub.OUT overvoltage condition exists and comparator C1 turns discharge transistor MPD on to discharge the output capacitor CL.
The above prior art LDO voltage regulator has several shortcomings. It does not directly detect the presence of an output overvoltage. Instead, it assumes that there is a V.sub.OUT overvoltage whenever error amplifier A1 drives the gate of output transistor MPX above V.sub.TRIP. But that assumption is not necessarily true. For example, if the feedback control loop is optimized for speed, then the output of error amplifier A1 most likely will exhibit some overshoot in its response to sudden changes in the load current. This could falsely trigger comparator C1 and cause it to turn on discharge transistor MPD. Even without the above mentioned overshoot on the output of error amplifier A1, a rapid decrease in the load current from, for example 100 percent to 50 percent of maximum, may cause comparator C1 to trip and turn on discharge transistor MPD. While this condition may produce a small overvoltage condition, turning on discharge transistor MPD does not actually help the overall recovery from the load current transient because the remaining load current quickly eliminates the V.sub.OUT overvoltage condition anyway.
The speed of response of discharge transistor MPD to an overvoltage condition at V.sub.OUT depends on both the speed of comparator C1 and the speed of error amplifier A1, the output of which is connected to the (-) input of comparator C1. Comparator C1 may be optimized for response speed, but error amplifier A1 has to drive the large gate capacitance of the large output transistor MPX, and therefore must be optimized for the best overall system operation and compensated for stability. If error amplifier A1 were infinitely fast, output transistor MPX would turn off before it had time to supply the extra charge into output capacitor CL and create a V.sub.OUT overvoltage. However, since error amplifier A1 is not infinitely fast it does introduce significant delay into the response of discharge transistor MPD to a V.sub.OUT overvoltage event. The delay through error amplifier A1 cannot be eliminated using the approach of U.S. PAt. No. 5,864,227 because the delay through error amplifier A is in fact the main reason that a V.sub.OUT overvoltage occurred.
It should be noted that the reference voltage V.sub.TRIP in prior art FIG. 1 is unrelated to the V.sub.OUT overvoltage. Instead, V.sub.TRIP is set to detect when output transistor MPX is sufficiently turned off that it can be inferred that a V.sub.OUT overvoltage condition exists. Specifically, the value of V.sub.TRIP is set using knowledge of a typical amount of V.sub.OUT overvoltage and the typical characteristics of output transistor MPX, rather than by considering the magnitude of a maximum allowable overvoltage at V.sub.OUT. The trip voltage V.sub.TRIP thus is not a function of how far V.sub.OUT is into an overvoltage condition in order to activate comparator C1. Instead, V.sub.TRIP is determined by the threshold voltage of output transistor MPX and V.sub.CC.
Furthermore, the LDO voltage regulator of prior art FIG. 1 is prone to small signal oscillations, wherein the voltage regulator alternately goes into and out of overvoltage correction operation when the output load is zero. This can be understood by considering a rapid load transition of I.sub.OUT from a heavy load to no load. The regulated output voltage V.sub.OUT will rise, and the output of error amplifier A1 will eventually saturate into the V.sub.CC rail in an attempt to turn off output transistor MPX as much as possible. This activates comparator C1, which then turns discharge transistor MPD on to discharge output capacitor CL. The speed and dynamics of the LDO voltage regulator of prior art FIG. 1 determine how quickly discharge transistor MPD will turn off after V.sub.OUT reaches its specified value of V.sub.REF multiplied by (R1+R2)/R1. The same delay through error amplifier A1 that caused the V.sub.OUT overvoltage in the first place will also delay the turn off of discharge transistor MPD. During this delay, discharge transistor MPD discharges output capacitor CL to a voltage below the specified value of V.sub.OUT. V.sub.OUT then is too low, so error amplifier A1 slews the gate of output transistor MPX until it turns on enough to increase V.sub.OUT. Since error amplifier A1 is recovering from its output being saturated into the V.sub.CC rail, it is very likely that V.sub.OUT will overshoot slightly and charge output capacitor CL too much, creating a new V.sub.OUT overvoltage. Since there is no load drawing current to remove the extra charge of output capacitor CL, the resulting V.sub.OUT overvoltage remains until the overvoltage correction circuit PD1 is activated again, and the cycle repeats and creates oscillations of V.sub.OUT.
Thus, there is an unmet need for an improved LDO voltage regulator which dissipates a reduced amount of power, and does not oscillate under no-load conditions.